Many different approaches are used to reduce power consumption at the circuit design level. Some of the main techniques are Transistor Sizing, Voltage Scaling, Voltage Islands, Multi-Threshold Voltages, and Power Gating. There is a negative effect to every power optimization technique used at the expense of performance or area. Rabaey (1996) states that the transistor sizing (TS) technique is used to adjust the size of each transistor (the smallest element in the digital system) or gate (group of transistors) for minimum power at the expense of the performance of the grid. Rabaey also states that the size of the transistor is only changed if its location is not critical and it will not affect the performance of the entire circuit. Another technique proposed by Pillai, Shin, and Arbor (2001) for power optimization is real-time dynamic voltage scaling (RT-DVS), dedicated to embedded computing systems. The RT-DVS technique exploits the hardware characteristics of processors to reduce power dissipation by lowering the supply voltage and operating frequency. Pillai, Shin, and Arbor also show that this RT-DVS algorithm closely approximates the theoretical lower bound of power consumption and can easily reduce power consumption by 20-40% in an embedded real-time system. On the other hand, the latter will be affected by decreasing the speed of the whole system when using a voltage scaling technique (Tawfik & Kursun 2009). Another technique called Voltage Island solves the problem of RT-DVS technique that different blocks can operate at different voltages to save power in a non-critical island/block (Puri et al. 2005). Puri et al. also show that voltage islanding may require the use of level changers (to change the voltage supply level) when two blocks...... middle of paper ......02). ACM. Puri, R., Kung, D. and Stok, L. (May 2005). Minimize power with flexible voltage islands. In Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on (pp. 21-24). IEEE. Tawfik, SA and Kursun, V. (2009). Low power, high speed multi-threshold voltage interface circuits. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 17(5), 638-645. Won, HS, Kim, KS, Jeong, KO, Park, KT, Choi, KM & Kong, JT (2003, August ). An MTCMOS design methodology and its application to mobile computing. In Low Power Electronics and Design, 2003. ISLPED'03. Proceedings of the 2003 International Symposium on (pp. 110-115). IEEE. Weng, SH, Kuo, YM, & Chang, SC (2012). Timing optimization in a sequential circuit by exploiting clock synchronization logic. ACM Transactions on Design Automation of Electronic Systems (TODAES), 17(2), 16.